text.skipToContent text.skipToNavigation
Product Variant Information section
Product Specification Section
Pricing Section

Stock: 668

On Order:Order inventroy details 400
Factory Stock:Factory Stock: 0
Factory Lead Time: N/A
Minimum Order: 1
Multiple Of: 1
Quantity Web Price
1 $2.65
30 $2.47
100 $2.41
250 $2.36
750+ $2.31
Total:

$2.65

USD
Attributes
Attributes Table
Memory Density 1Mb
Memory Organization 64 K x 16
Supply Voltage-Nom 4.5V to 5.5V
Access Time-Max 12ns
Temperature Grade Commercial
Features and Applications

The AS7C1026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications.

When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2).

To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode.

The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The device is packaged in common industry standard packages.

A 1MB 5.0V Fast Asynchronous Alliance product that has a 64K x16 configuration, with commercial temperature range (0˚C to 70˚C), and a 44-pin SOJ package. The part supports 12 nanoseconds speeds and is RoHS compliant.